1. Field of the Invention
The invention relates in general to a semiconductor fabricating method, and more particularly to a fabricating method for a teal oxide semiconductor (MOS).
2. Description of the Related Art
As integrated circuits become more complicated and their function becomes more powerful, the required density of transistors in an integrated circuit increases correspondingly. The high density of these complex integrated circuits cannot be easily achieved by simply decreasing a layout according to device proportions of the integrated circuits. The device size must be decreased by a design rule and with consideration for possible change in the physical characteristics of the device. For example, channel length of a MOS transistor cannot be reduced infinitely. Reduction size may cause a short channel effect. Once the short channel effect happens, a punchthrough problem is likely to occur. The punchthrough problem occurs due to current leakage when the MOS transistor is switched off. The conventional solution to the punchthrough problem is to increase punchthrough voltage, in a procedure such as a punchthrough stopper implantation or a halo implantation.
FIG. 1 and FIG. 2 respectively explain the related positions of an anti-punchthrough region and a MOS formed by conventional methods.
In FIG. 1, an N-type MOS is taken as an example. In a typical punchthrough stopper implantation, P-type impurities are implanted in the substrate 100 before forming a gate 106 and a source/drain region 120. A heavily doped anti-punchthrough region 114 is formed in the substrate 100 below the surface-channel region 112 between the source/drain region 120.
In FIG. 2, a tilt-angle halo implantation step is performed after a gate 206 and a source/drain extension 210a are formed. P-type impurities are locally implanted in the substrate 200. An anti-punchthrough region 214, which is connected to the source/drain extension 210a, is formed in the substrate 200. In contrast with the anti-punchthrough region 114 formed by punchthrough stopper implantation, the anti-punchthrough region 214 formed by halo-implantation, which region connects to the extension region 210a, has higher anti-punchthrough ability. Hence, the anti-punchthrough region 214 is more suitable than the anti-punchthrough region 114 for a MOS occupying a small planar area.
A depletion region usually exists at an interface of the interchangeable source/drain region and the substrate due to, for example, a depletion of electron holes for a P-type substrate. This depletion region behaves like a capacitor and contributes a junction capacitance. The junction capacitance is larger if the depletion region is larger. The depletion region is larger if the dopant density is larger or junction contact area is larger. A higher dopant density also needs a higher dopant density in the anti-punchthrough region formed by halo-implantation in order to reduce a short channel effect. However, another depletion region also exists at an interface between the anti-punchthrough region formed by halo-implantation and the source/drain region. Since the anti-punchthrough region carries higher dopant density, it results in a higher junction capacitance. It is natural for an AC circuit that the junction capacitance can reduce an alternative-current (AC) operation speed. In addition, the gate oxide layer also induces an oxide capacitor, which is coupled with the junction capacitor in series. The oxide capacitor increases the junction capacitance and causes a slower AC operation speed.